A common concern with semiconductor memories is the reliability of the memory. Of particular concern with memories that are electrically programmable is the memory's endurance or number of cycles which such memories must be erased and re-programmed. For example, electrically erasable programmable read only memories (EEPROMs) require an endurance of many thousands of cycles in some applications. Although the intrinsic endurance of a memory is greater than one million cycles, the actual endurance of a typical memory is limited to approximately ten thousand cycles. The relatively low endurance of memories results from random defects in transistor gate oxides and thin tunnel dielectrics commonly existing in most semiconductor processes. Therefore, in applications requiring a memory with high endurance or reliability, a memory must be fabricated with either redundancy or error checking and correction (ECC) circuitry. Known redundancy techniques other than ECC circuitry which are used in EEPROMs use either a one hundred percent duplication of all memory cells or a one hundred percent duplication of all arrays of the memory. A disadvantage with the known redundancy techniques is the additional size required for duplicate memory cells and many applications do not require one hundred percent redundancy. With respect to the ECC approach, less memory circuitry is duplicated but additional circuitry and control functions are required to create a large increase in the overhead of the system utilizing the memory.